1. Field of the Invention
The present invention relates to an effective technology applied in semiconductor device comprising an SRAM (Static Random Access Memory).
2. Description of the Background Art
An example of a conventional SRAM is shown in FIG. 5.
The SRAM is a volatile semiconductor device disposing a memory cell at the intersection of a complementary data line (bit line) BIT, BIT, and word lines W1, W2 arranged in a matrix form. The memory cell is composed of a flip-flop circuit FFP, and two access transistors A1P, A2P. By this flip-flop circuit FFP, two cross-coupled memory nodes N1, N2 are composed, and the SRAM possesses a bistable state, that is, (level of node N1, level of node 2) are (High, Low) or (Low, High), and as far as a specified external supply voltage V.sub.cc is applied, the bistable state is maintained, in principle. The access transistor A1P (A2) has its one semiconductor region (second electrode) connected to the memory node (input, output terminal of the flip-flop circuit FFP) N1 (N2), and has its other semiconductor region (first electrode) connected to the complementary data line BIT (BIT). The gate electrode (third electrode) of the access transistor A1P (A2P) is connected to the word line W1 (W2), and conduction and non-conduction of the access transistor A1P (A2) are controlled by this word line W1 (W2).
When writing in data, selecting the word lines W1,W2, both access transistors A1P and A2P are made to conduct, and a voltage is applied by force to the bit line pair in response to desired logic value, and thereby a monostable state of the flip-flop circuit FFP is realized.
When reading out data, on the other hand, by conducting the access transistors (AP1, AP2), the potentials of the memory nodes (N1, N2) are transmitted to the bit lines (BIT, BIT).
The flip-flop circuit FFP is composed of two driver transistors D1P, D2P, and two load elements R1, R2. As shown in FIG. 5, the driver transistor D1P and load element R1, and the driver transistor D2P and load element R2 respectively form inverters. Concerning the driver transistor D1P (D2P), its drain region (third electrode) is connected to the semiconductor region (second electrode) of the corresponding access transistor A1P (A2P), and its source region (fourth electrode) is connected to the ground line (V.sub.EE line). The gate electrodes of the driver transistors D1P, D2P are connected to the semiconductor region (second electrode) of the other access transistors A2P, A1P. Concerning the load element R1 (R2), one is connected to the semiconductor region (second electrode) of the corresponding access transistor A1P (A2P), and the other is connected to a power supply line 3 of the memory cell.
In the conventional semiconductor device, herein, in order to further advance the degree of integration and enhance the performance, it is necessary to reduce the transistor size, in particular, the gate length of MOS transistor. In the SRAM, too, by reducing the gate length, the occupied area in the memory cell is decreased, and higher degree of integration is realized. However, as the gate length is shortened, the channel length is also cut short, and hence unless the supply voltage is lowered proportionally, it gives rise to the problem of deterioration of MOS transistor characteristic due to hot carrier effect.
Accordingly, along with the trend of higher degree of integration, usually, the external supply voltage V.sub.cc is stepped down by using a down converter circuit, and a voltage lower than the external supply voltage V.sub.cc is applied to the power source line, word line and bit line of the memory cell, and such constitution is also employed in the SRAM shown in FIG. 5. That is, as shown in FIG. 5, the voltages stepped down from the external supply voltage V.sub.cc by the portion of threshold voltages V.sub.Q1th to V.sub.Q5th of N-channel MOS transistors Q1 to Q5 as step-down transistors are supplied to bit line BIT, word line W1, and power source line 3, word line W2 and bit line BITof the memory cell, respectively.
The prior art described above can prevent occurrence of hot carrier effect by the decline of external supply voltage due to higher degree of integration. It brings about newly, however, the following problems.
That is, the lower the supply voltage applied to the memory cell, the more difficult is the stable action of the memory cell. This point is described below by referring to the input and output transmission characteristic of a pair of cross coupled inverters for forming a flip-flop circuit of the memory cell.
The input and output transmission characteristic shown in FIG. 6 becomes as shown in FIG. 7. Therefore, the input and output characteristic of the pair of inverters shown in FIG. 8 is expressed in FIG. 9. To function as flip-flop, it is required to have two stable points expressed by S1 and S2 in FIG. 9. In order that the memory cell may withstand practical use, it is necessary to design so that the region enclosed by two curves in the diagram may be sufficiently wide. Accordingly, the diameter of the circle shown in the diagram is used as the index, and it is called SNM (Static Noise Margin).
Nextly, the transmission characteristic of the memory cell MC of which the equivalent circuit is shown in FIG. 10 is described below.
Usually, in standby state, access transistors (A1P, A2P) are non-conductive, and therefore the inverter of the memory cell MC is composed of a driver transistor and load elements. At this time, as shown in FIG. 11, the load elements (R1, R2) are high in impedance, and the inclination of the transitional part of the inverter output is steep, the SNM is large, so that the data is held stably.
By contrast, when reading out data, in the memory cell, the access transistors are conductive, and a column current flows from the bit line into the low side memory node. That is, it is equivalent to a constitution in which a load of low impedance is connected parallel to the load elements, and the inverter of the memory cell must be handled as an enhancement mode NMOS comprising access transistors as load. When reading out, accordingly, as shown in FIG. 12, the gain of the inverter is considerably lowered as compared with the time of stand-by. In other words, the inclination of the transitional part of the inverter output becomes moderate. Consequently, the potential of the other high side memory node is lowered from the supply voltage level at the time of standby to (supply voltage-threshold voltage V.sub.th of access transistor), and the SNM is extremely lowered temporarily. This time is the most risky moment for the memory cell, and the bistable state is lost and the data may be broken unless a sufficient SNM is maintained. Usually, to expand the SNM, the conductance ratio of the driver transistor to the access transistor, also known as the beta ratio, is increased, and the gain of the inverter is made large. As a result, the inclination of the transitional part of the inverter output becomes steep. As the degree of integration is advanced, however, because of the necessity of reduction of layout area, it is difficult to increase the size of the driver transistor, in particular its gate width. Hence, to advance the degree of integration, the method of improving by increase of the beta ratio cannot be employed.
In writing action, incidentally, the access transistor conducts, and pulls down one bit line to L level by force, so that the corresponding other memory node is see to Low by force. This point is described below by referring to FIG. 13 showing the inverter transmission characteristic at the time of writing.
First, suppose the memory cell MC is stable at intersection S2, that is, (node N1, node N2)=(L level, H level). To obtain reverse data, (node N1, node N2)=(H level, L level), the bit line BIT of node N2 side is pulled down to L level by force. As a result, the inverter characteristic curve of N1 input and N2 output changes from a curve C1 to a curve C2. Hence, the stable point is only an intersection S1' of two curves to be in monostable state, so that data is rewritten.
Right after writing, however, the potential of the high side memory node is raised only up to (supply voltage-threshold voltage V.sub.th of the access transistor), and the problem is that the data is likely to be destroyed by external noise, .alpha.-ray, or the like.
The problems become more serious when the influence of voltage drop by the portion of threshold voltage V.sub.th of the access transistor becomes larger due to lowering of supply voltage, and hence the stability of memory cell is extremely lowered unless the threshold voltage V.sub.th is reduced proportionally. Yet, if the threshold voltage V.sub.th is decreased, the sub-threshold current increases, which gives rise to a new problem of increase of standby current at the time of standby (in standby, the bit line is in High level, and the current flows from the Low side memory node through the driver transistor). It is hence difficult to reduce the threshold voltage V.sub.th proportionally.